1. Field of the Invention
The present invention relates to a method for producing a semiconductor device, and more particularly to a method for reducing a mask step in a CMOS production process.
2. Description of the Related Art
In a CMOS production process, following methods have been used as a method for reducing a mask step in forming a gate electrode on a semiconductor substrate, and forming a well, and source and drain regions in the semiconductor substrate by ion implantations.
FIGS. 1A to 1C show a method disclosed in Japanese Unexamined Patent Publication No. 4-25168 (hereinafter, referred to as Document 1). First, a P well 101 is formed in a region (NMOS region) in which an NMOS transistor is formed, and an N well 102 is formed in a region (PMOS region) in which a PMOS transistor is formed, and gate electrodes 104a and 104b are formed on a gate insulation film 103 in the NMOS region and the PMOS region, respectively (FIG. 1A). Thereafter, N-type impurity ions are implanted in a whole surface. In this manner, N-type source and drain regions 105a are formed in the P well, while at the same time, N-type impurity regions 105b are formed in a region in the N well in which source and drain regions are formed.
Then, the NMOS region is covered with a mask, and P-type impurity ions are implanted only into the PMOS region. Thus, the P-type source and drain regions 106 are formed in the P well, and as shown in FIG. 1C, the MOS transistor is formed in each of the NMOS region and the PMOS region.
Next, FIGS. 2A to 2C show a method disclosed in Japanese Unexamined Patent Publication No. 4-188762 (hereinafter, referred to as Document 2). First, a P well 201 is formed in an NMOS region, an N well 202 is formed in a PMOS region, and a gate electrode material 204 is deposited on a whole surface of a gate insulation film 203 (FIG. 2A). Thereafter, the PMOS region, and the NMOS region in which a gate electrode is formed are covered with a mask, and a gate electrode 204a of the NMOS transistor is formed, and N-type source and drain regions 205 are formed in the P well 201 by an ion implantation of an N-type impurity with the same mask pattern (FIG. 2B).
Then, the NMOS region, and the PMOS region in which a gate electrode is formed are covered with a mask, and a gate electrode 204b of the PMOS transistor is formed, and P-type source and drain regions 206 are formed in the N well 202 by an ion implantation of a P-type impurity with the same mask pattern. In this manner, as shown in FIG. 2C, a MOS transistor is formed in each of the NMOS region and the PMOS region.
According to the production method disclosed in Document 1, among steps such as (1) the step of forming the N well, (2) the step of forming the gate electrode, and (3) the step of forming the source and drain regions, in the PMOS region, and (4) the step of forming the P well, (5) the step of forming the gate electrode, and (6) the step of forming the source and drain regions, in the NMOS region, the steps (2) and (5) of forming the gate electrodes are performed with the common mask pattern at the same time, and a mask pattern for the step (6) of forming the source and drain regions of the NMOS transistor is not necessary, so that the required number of mask steps is four.
In addition, according to the production method disclosed in Document 2, the step (2) of forming the gate electrode in the PMOS region, and the step (6) of forming the source and drain regions in the NMOS region are performed with the common mask pattern, and the step (3) of forming the source and drain regions in the PMOS region and the step (5) of forming the gate electrode in the NMOS region are performed with the common mask pattern, so that the required number of mask steps is four.